Comparing Different Fault Models Using VERIFY1

Fault injection is a widely used method for evaluating dependable systems. The intention of this paper is to compare typical fault models used for fault injection regarding their accuracy in predicting the reliability of the system. For this purpose, we set up an experiment by injecting faults in a VHDL model of the DP32-processor at gate-level, pin-level and at register-transfer level. The experiment has been performed by using the simulation based fault injector VERIFY (VHDL-based Evaluation of Reliability by Injecting Faults efficientlY). The differences in the predicted mean failure rate of the system will be shown and a comparison of system’s behavior after fault injection will be presented. The results demonstrate that faults have to be injected at least at gate-level in order to represent the correct timing behavior of the digital system after the fault has been injected and help the designer of a dependable system to find the weak components.